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Test Number : 000-933
Test Name : IBM Tivoli Netcool/OMNIbus V7.2 Implementation
Vendor Name : IBM
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IBM tricks

IBM Debuts Power10; Touts New memory Scheme, security, and Inferencing | 000-933 practice questions and PDF Questions

IBM these days introduced its next technology Power10 microprocessor, a 7nm gadget manufactured by way of Samsung. The chip elements a new microarchitecture, large new reminiscence help, PCIe Gen 5 connectivity, hardware enabled security, mind-blowing power efficiency, and a number of other improvements. Unveiled at the annual scorching Chips convention (virtual this 12 months) Power10 received’t turn up in IBM techniques until this time subsequent 12 months. IBM didn’t expose when the chip can be attainable to different techniques makers.

IBM says Power10 presents a ~3x efficiency gain and ~2.6x core efficiency benefit over Power9. No benchmarks in opposition t non-IBM chips were introduced. Power9, of route, turned into brought in 2017 and manufactured by using global Foundries on a 14nm procedure. whereas the move to a 7nm method offers many of Power10’s features, there are additionally significant new elements, no longer least what IBM calls Inception memory that allows for Power10 to entry as much as “multi petabytes” of pooled reminiscence from distinct sources.

“You’re able to kind of trick a equipment into pondering that reminiscence in an extra device belongs to this device. It isn’t like natural [techniques] and doing an RDMA over InfiniBand to get entry to people’s memory. here's programs operating on my desktop [that] can do load-store-access without delay, coherently,” stated William Starke, IBM unusual engineer and a Power10 architect in a pre-briefing. “They use their caches [to] play with reminiscence as if it’s in my device, in spite of the fact that it’s bridged by means of a cable over to one more system. If we’re the use of short-reach cabling, they are able to in reality try this with best 50-to-one hundred nanoseconds of extra latency. We’re no longer speaking adding a microsecond or something such as you might have over and RDMA.”

IBM is promoting Inception as an important success.

“HP got here out with their large issue just a few years in the past. They called it The computing device and it become going to be their approach of revolutionizing things largely by means of disaggregating memory. Intel you’ve viewed from their charts talking about their Rack Scale architectures [that] they’re evolving toward. neatly, this is IBM’s edition of this and they now have it nowadays, in silicon. they are asserting we're capable of take issues backyard of the system and aggregate the distinctive programs together to directly share reminiscence,” referred to Starke.

Inception is only one of many enjoyable aspects of Power10, which has roughly 18 billion transistors. IBM plans to present two core types – 4 SMT (simultanous multi-threaded) cores and 8 SMT cores; IBM focused on the latter in nowadays’s presentation. There are 16 cores on the chip and on/offchip bandwidth by way of the OMI interface or PoweAXON (for adding OpenCAPI accelerators) or PCIe5 interface, all of which can be shown delivering up to 1 terabyte per sec on IBM’s slides.

CXL interconnect is not supported by means of Power10, which is perhaps marvelous given the more and more favorable comments about CXL from IBM over the last yr.

Starke spoke of as a part of a Slack conversation tied to hot Chips, “Does POWER10 guide CXL? No, it does not. IBM created OpenCAPI as a result of they trust in Open, and we've 10+ years of journey in this area that they wish to share with the business. They comprehend that an uneven, host-dominant connect is the handiest method to make these items work across assorted companies. we're inspired to peer the same underpinnings in CXL. It’s open. It’s asymmetric. So it’s constructed on the appropriate foundations. we're CXL members and they want to carry their know-how into CXL. but at the moment, CXL is a few years behind OpenCAPI. unless it catches up, they cannot have enough money to take a step backwards. at the moment OpenCAPI offers a good opportunity to get in entrance of issues which will become greater mainstream as CXL matures.”

below is the block diagram of IBM’s new Power10 chip showing main structure features.

The manner reduce does play position in enabling to IBM to offer two packaging alternatives proven beneath (slide below).

“We’re providing two models of the processor module and have been in a position to try this basically because of the power effectivity good points,” spoke of Starke. “We’re bringing out a single chip module. there's one Power10 chip and exposing all those high bandwidth interfaces, so very excessive bandwidth per compute class of features. [O]n the higher correct you could see [it]. They build a sixteen-socket, massive device that’s very robustly scalable. We’ve loved success over the ultimate a few generations with this classification of offering, and Power10 is going to be no distinct.

“On the backside you see something a bit new. they are able to really take two Power10 processor chips and cram them into the identical kind aspect where they used to put just one Power9 processor. We’re taking 1200 square millimeters of silicon and putting it into the identical form factor. That’s going to be very valuable in compute-dense, energy-dense, volumetric house-dense cloud configurations, where they will construct methods ranging from one to 4 sockets where these are twin chip module sockets as proven there on the reduce appropriate,” he spoke of.

It might be wonderful to peer what sort of traction both distinct offerings benefit amongst non-IBM methods builders in addition to hyperscalers. widely IBM is positioning Power10 as a strong fit for hybrid cloud, AI, and HPC environments. Hardware and firmware enhancements were made to support protection, containerization, and inferencing, with IBM pointedly suggesting Power10 will be capable of deal with most inferencing workflows in addition to GPUs.

speakme about protection, Satya Sharma, IBM Fellow and CTO, IBM Cognitive programs, noted “Power10 implements clear reminiscence encryption, which is reminiscence encryption with none efficiency degradation. when you do reminiscence encryption in software, it continually results in performance degradation. Power10 implements transparent hardware reminiscence encryption.”

Sharma stated identical facets for containers and acceleration cryptographic specifications. IBM’s respectable announcement says Power10 is designed to deliver hardware-enforced container protection and isolation optimized with the IBM firmware and that Power10 can encrypt statistics 40 p.c faster than Power9.

IBM additionally stories Power10 supplies a 10x-to-20x capabilities over Power9 on inferencing workloads. memory bandwidth and new guidance helped obtain these good points. One instance is a new special goal-developed matrix math accelerator that become tailor-made for the demands of computing device gaining knowledge of and deep getting to know inference and contains lots of AI records kinds.

Focusing for a moment on dense-math-engine microarchitecture, Brian Thompto, exceptional engineer and Power10 dressmaker, noted, “We additionally concentrated on algorithms that were hungry for flops, such as the matrix math utilized in deep researching. each core has in-built matrix math acceleration and successfully performs matrix outer product operations. These operations had been optimized throughout a big range of statistics forms. Recognizing that quite a lot of precisions can be optimum suited for selected computing device gaining knowledge of algorithms, they covered very extensive aid: double precision, single precision, two flavors of half-precision doing both IEEE and bfloat16, in addition to reduced precision integer 16-, eight-, and four-bit. The outcome is 64 flops per cycle, double precision, and up to 1 ok flops per cycle of decreased precision per SMT core. These operations were tailor made to be efficient whereas applying computing device studying.

“on the socket level, you get 10 times the performance per socket for double and single-precision, and using decreased precision, bfloat16 speeded up to over 15x and int8 inference sped up to over 20x over Power9,” Thompto delivered.

more widely, he said, “we've a number of new capabilities in ISA version three.1. here's the brand new guideline set structure that helps Power10 and is contributed to the OpenPOWER groundwork. the brand new ISA supports 64-bit prefixed instructions in a chance-pleasant method. here is moreover the basic manner that we’ve delivered 32-bit guidance for many many years. It opens the door to including new capabilities comparable to including new addressing modes as well as offering prosperous new opcode area for future enlargement.”

hyperlink to scorching Chips: https://www.hotchips.org

hyperlink to IBM weblog: https://newsroom.ibm.com/Stephen-Leonard-POWER10

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