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Administering HP Converged Infrastructure Solutions

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Test Number : HP0-D24
Test Name : Administering HP Converged Infrastructure Solutions
Vendor Name : HP
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Intel Xe-HP graphics: Early Samples present 42+ TFLOPs of FP32 efficiency | HP0-D24 braindumps and boot camp

some of the promises that Intel has made with its new Xe GPU family is that in its quite a lot of types it is going to cater to makes use of starting from built-in snap shots the entire manner up to the high efficiency compute models needed for super-dense supercomputers. This ability help for the kinds of calculations involved in fundamental photographs, advanced images, ray tracing, AI inference, AI practising, and the compute that goes into molecular modelling, oil-and-fuel, nuclear reactors, rockets, nuclear rockets, and all the other massive questions the place extra compute presents more capabilities. Sitting close the properly of Intel’s offerings is the Xe-HP architecture, designed to offer excessive performance GPUs for commonplace server and business deployments.

over the past couple of weeks Intel has provided one of the vital first technical particulars of Xe-HP, following Raja Koduri displaying it off across his social media profiles. They be aware of that it's designed to be a modular structure, with distinct chiplets related collectively the use of Intel’s Embedded Multi-Die Interconnect Bridge know-how. They also be aware of, due to disclosures made at Intel’s architecture Day, that it is decided to be developed on Intel’s 10nm enhanced SuperFin (10ESF, formerly 10++, previously 10+++) manufacturing procedure, which they accept as true with to be a late 2021 manner. Raja Koduri promised throughout the architecture Day presentation that Xe-HP (and Xe-HPG) may be attainable in 2021.

Intel explained that the modular Xe-HP design will scale from one to four tiles, and the thought of Xe-HP became to ‘scale everything’, corresponding to execution gadgets, frequency, bandwidth, IPC, and math capabilities. They expect that every tile may have direct entry to some on-chip memory as well – in fact scaling up each point of a chip – besides the fact that children how the chip's HBM2E is allocated hasn't been demonstrated. The point of the product is that it's designed for the records-middle, so there needs to be a mix of media compute as well as raw compute, overlaying all kinds of uses circumstances.

As a part of the demonstration all the way through architecture Day, Intel additionally showcased that they’ve been operating some benchmarks on the early silicon within the labs. via early silicon, they suggest that these aren’t working at the final frequencies, this isn’t closing firmware, and the utility stack still has a method to head, so obviously there are optimizations at every stage.

First, Intel showed that a single tile of Xe-HP cannot most effective transcode one 4K60 video in real time, but ten. in the demonstration that they had the FFmpeg output, showing that the demo become converting each video from 5332 kb/s standard right down to 3000 kb/s general (6000 kb/s max).

For compute, Intel provided the following performance numbers, given as peak GFLOPs of FP32 math the usage of the OpenCL-based CLPeak benchmark.

One Tile: 10588 GFLOPs (10.6 TF) of FP32

Two Tile: 21161 GFLOPs (21.2 TF) of FP32 (1.999x)

four Tile: 42277 GFLOPs (forty two.3 TF) of FP32 (3.993x)

We additionally get some additional information from the video of Xe-HP. The checks were executed on Linux, and really all completed on a edition of the quad-tile chip, but made to run in 1T/2T/4T modes. this is why when looking at the video they can see all three types are working at 1300 MHz. The string used for the chip is ‘XeHP HD graphics NEO’ as well.

The video also indicates that a single tile has 512 ‘compute units’, whereas the dual tile has 1024 compute instruments and the quad-tile has 2048 compute contraptions. And while Intel hasn't officially claried what "compute units" suggest during this context, the performance figures all but verify that or not it's counting Intel's Execution devices. according to the given GFLOPs, the stated clock velocity, and the Xe structure's eight pipes per Execution unit with dual FMAs, Intel's performance figures map to 512/1024/2048 EUs respectively. that might mean that each and every one would have:

One Tile: 512 EUs = 4096 ALUs (+ 1024 prolonged Math ALUs)

Two Tile: 1024 EUs = 8196 ALUs (+ 2048 prolonged Math ALUs)

4 Tiles: 2048 EUs = 16384 ALUs (+ 4096 prolonged Math ALUs)

here is assuming that the Execution Unit structure of eight+2 from Xe-LP remains. They recognize that HP will support new XMX guidance for matrix math, in addition to AI-linked quantization ranges and FP64 too. Which Intel's hot Chips presentation has established may be carried out in the EUs as extra genuine blocks.

There turned into also a shot of the rear of an Xe-HP die, which Raja has proven off right through his scorching Chips keynote as smartly. they are able to play a online game of count number the pins.

Intel Xe-HP 4-Tile Rear

Intel believes it's achieving close linear scaling in compute performance across its multi-tile strategy – as a minimum up to 4T using CLPeak, a benchmark designed to measure a GPU's highest compute throughput. There’s nothing here to assert about tile-to-tile bandwidth scaling, or if this multi-tiling method and NUMA association of tiles has knock-on consequences for memory-constrained or sparse math – Intel’s intention was without difficulty to exhibit that the hardware is operating and how much peak compute efficiency it could offer. There’s additionally no note on vigour consumption either, or charge, youngsters within the presentation Intel says that the purpose right here is to offer the equal of a rack-scale transcoding equipment in a single chip with most excellent-in-type TCO, winning on performance-per-watt-per-greenback.

Xe-HP is decided to be obtainable in 2021 for the commercial enterprise market.

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